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19-1180; Rev 0; 6/98
Mobile-Radio Analog Controller
________________General Description
The MAX1007 is a multifunctional integrated circuit designed for high-performance mobile radios. It includes one 8-bit analog-to-digital converter (ADC), and two 7-bit and two 6-bit digital-to-analog converters (DACs) for functions including radio-frequency (RF) power sensing and antenna-diversity selection. The ADC provides for power sense, receive-signal strength intensity (RSSI) measurements and system supervision. In the power-sense mode, the ADC converts the power-sensing circuitry signal (representing either the transmitted (Tx) or received (Rx) RF power) into a digital code, ensuring optimum Tx power setting and Rx signal analysis. An additional direct input to the ADC provides for system-supervision measurements, such as power-supply voltages, battery voltage, and temperature. Four DAC blocks typically control DC levels in radios. As part of the Maxim PWT1900 chip set, the two 7-bit DACs control the gain settings and the two 6-bit DACs control the varactor diodes to tune a TCXO and bias a GaAs amplifier. Each DAC register and output can be updated independently, providing maximum flexibility. For antenna diversity, a magnitude-comparison circuit captures and compares two peak signals. A latched logic-comparator output reveals which signal has the largest magnitude. The MAX1007 also includes an onboard voltage reference for the ADC and DACs. The MAX1007 offers a high level of signal integrity with minimal power dissipation. Single-supply operation ranges from +2.85V to +3.6V. To further save power, there are two shutdown modes: standby and total shutdown. Standby is a partial shutdown that keeps the bandgap reference and the 2.4V reference generator active. Total shutdown disables all circuit blocks except the serial interface, reducing supply current to less than 1A. The MAX1007 is available in a 24-pin SSOP and is specified for commercial and extended temperature ranges.
____________________________Features
o Multi-Input 8-Bit ADC o Two 7-Bit DACs with Buffered Outputs o Two 6-Bit DACs: Buffered/Unbuffered o Power-Sense Conditioning Circuitry o RSSI Measurement o Antenna-Diversity Circuitry o Internal Reference o Serial-Logic Interface o +2.85V to +3.6V Single-Supply Operation o Two Shutdown Modes
MAX1007
Ordering Information
PART MAX1007CAG MAX1007EAG TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 24 SSOP 24 SSOP
Pin Configuration appears at end of data sheet.
Functional Diagram
PSDWDW PSDCTRL
PREAMBLE-SWITCHED DIVERSITY DUAL T/H D FLIP-FLOP BANT
REF RSSI PKWDW ADC CTRL RPS FPS1 FPS2 CH1 PEAK DETECTOR POWER SENSE PSOUT ADC SERIAL INTERFACE CH0 CS SCLK DIN DOUT SDG
________________________Applications
PWT1900 Wireless Communications: Cellular Radios PCS Radios PMR/SMR WLL
SDAC XDAC GDAC
POWER SENSE CIRCUITRY SDAC XDAC GDAC 7 6 6
MAX1007
REFERENCE
VREF
KDAC
KDAC
7 PSBIAS
________________________________________________________________ Maxim Integrated Products
1
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Mobile-Radio Analog Controller MAX1007
ABSOLUTE MAXIMUM RATINGS
AVDD or DVDD to AGND or DGND...........................-0.3V to +6V Digital Inputs to DGND.............................................-0.3V to +6V Analog Inputs to AGND............................................-0.3V to +6V REF to AGND............................................................-0.3V to +6V AGND to DGND ................................................................. 0.3V AVDD to DVDD .................................................................... 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) SSOP (derate 8.0mW/C above +70C) ......................640mW Operating Temperature Ranges MAX1007CAG.....................................................0C to +70C MAX1007EAG ..................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER POWER-SUPPLY REQUIREMENTS Supply Voltages AVDD, DVDD RxEN = 0, TxEN = 1; AVDD = DVDD = 3V; PKWDW = ADCCTRL = DGND RxEN = 0, TxEN = 1; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state B on Figure 1 2.85 3.0 3.6 V SUPPLY CURRENTS [I(AVDD) + I(DVDD)] (Note 1) CONDITIONS MIN TYP MAX UNITS
Transmit Mode 1: All DACs, Ref, RefBuf Active Transmit Mode 2: All DACs, PGA, REF, Peak Detector, PSBIAS, ISOURCE, RefBuf Active Transmit Mode 3: All DACs, PGA, REF, Peak Detector, PSBIAS, ISOURCE, RefBuf, ADC Active Receive Mode 1: KDAC, XDAC, Ref, RefBuf Active Receive Mode 2: KDAC, XDAC, Peak Detector, RSSI Buffer, Ref, RefBuf Active Receive Mode 3: KDAC, XDAC, ADC, Peak Detector RSSI Buffer, Ref, RefBuf Active Receive Mode 4: KDAC, XDAC, ADC, RSSI Buffer, Ref, RefBuf, PSD Circuit Active Standby: XDAC, GDAC, Ref, RefBuf Active
Total Shutdown
1.8
5.0
mA
4.7
mA
RxEN = 0, TxEN = 1; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state C on Figure 1
12.2
32
mA
RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW = ADCCTRL = DGND RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state B on Figure 1
1.24
3.5
mA
2.95
mA
RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state C on Figure 1
11.2
31
mA
RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state B on Figure 1. PSDWDW and PSDCNTRL as per state D on Figure 2 RxEN = 1, TxEN = 1; AVDD = DVDD = 3V RxEN = 0, TxEN = 0; AVDD = DVDD = 3V; ADCCTRL = PSDCTRL = PKWDW = PSDWDW = DGND; SCLK not active, either high or low
4.07
10.5
mA
1.24
3.5
mA
1
10
A
2
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Mobile-Radio Analog Controller
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER XDAC Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Full-Scale Output Swing Output Resistance GDAC Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Output Slew Rate Full-Scale Output Swing Full-Scale Step Response Time SDAC, KDAC Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Output Slew Rate Full-Scale Output Swing Full-Scale Step Response Time Power-Up Time from Standby ADC Resolution Input Signal Range Differential Nonlinearity Integral Nonlinearity Conversion Time Offset Error Gain Error Reference Voltage ADC Power-Up Time from Standby 1.74 With respect to VREF 2 5 1.028 VREF = 1.028V (typ) VREF = 1.028V (typ) 1 5.2 8 0 VREF 1 Bits V LSB LSB s LSB LSB V s (Note 2) CL = 30pF, RL = 40k RL = 40k CL = 30pF, RL = 40k, settling to 2% of final value CL = 30pF, RL = 40k, settling to within 2% of final value 2.1 2 < code FS 2 < code FS 1 1 10 0.1 2.42 4 4 2.75 7 1 Bits LSB LSB LSB %FSR V/s V s s RL = 40k CL = 30pF, RL = 40k, settling to 5% of final value 2.1 2 < code FS 2 < code FS CL = 30pF, RL = 40k (Note 2) 1 1 10 0.1 2.42 4 2.75 6 1 Bits LSB LSB LSB %FSR V/s V s (Note 2) No resistive load 2.1 2 < code FS 2 < code FS 1/2 1 10 2.42 30 2.75 6 1 Bits LSB LSB LSB %FSR V k CONDITIONS MIN TYP MAX UNITS
MAX1007
3
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Mobile-Radio Analog Controller MAX1007
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER RSSI CIRCUIT Lowpass-Filter Time Constant Minimum Peak Level Detected Maximum Peak Level Detected TRANSMIT POWER SENSE Offset Voltage Power-Sense Amp Gain (PGA) Current Source Pull-Down Input Resistance REFERENCE Output Voltage PS Bias Voltage Output PS Bias Sink Current Internal DAC Reference SERIAL-LOGIC INTERFACE Digital Inputs (CS, SCLK, DIN, PKWDW, ADCCTRL, PSDWDW, PSDCTRL) Input Voltage High Input Voltage Low Input Current Input Resistance Inpt Capacitance Output Voltage High Output Voltage Low DIN Valid to SCLK Setup DIN to SCLK Hold CS Low to SCLK High CS Low to DOUT Valid SCLK High to DOUT Valid SCLK Pulse Width High SCLK Pulse Width Low CS High to DOUT Disable ADC Data Output Delay After End of ADC Conversion (Figure 4b) VIH VIL IIN RIN CIN VOH VOL t1 t2 t3 t4 t5 t6 t7 t8 t9 CL = 20pF 500 200 200 434 434 100 Excluding PSDCTRL, PSDWDW PSDCTRL, PSDWDW Digital inputs CL = 20pF, RL = 100k CL = 20pF, RL = 100k 100 0 20 100 150 VDD - 0.4 0.4 20 10 0.7VDD 0.3VDD 1 V V A k pF V V ns ns ns ns ns ns ns ns ns RS in series with CL, CL = 1nF, 200 RS 1k RS in series with CL, CL = 1nF, 200 RS 1k 200 2.42 0.96 1.028 1.87 1.1 V V A V RPS, FPS1, FPS2 to ADC input Forward transmit Reflected transmit, class 1 Reflected transmit, classes 2, 3, 4 Figure 3b RPS, FPS1, FPS2 pulled to AGND when not selected 50 150 -0.53 -6 -0.44 100 200 180 A V/V mV 10 20 100 VREF 300 s mV V SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital Outputs (DOUT, BANT, SDG)
TIMING SPECIFICATIONS (Figure 4)
4
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Mobile-Radio Analog Controller
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ADCCTRL Low to RF input PSDWDW Low to BANT Valid SCLK Duty Cycle Note 1: All digital inputs at DVDD or DGND. Note 2: All DACs use an internal reference voltage of 2.42V. SYMBOL t10 t11 CONDITIONS RF input on RSSI, RPS, FPS1, FPS2, or PSBIAS, (Figure 4c) CL = 20pF (Figure 4c) MIN TYP 200 100 50 MAX UNITS ns ns %
MAX1007
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (Tx MODE)
MAX1007-02 MAX1007-01
DIFFERENTIAL NONLINEARITY
0.5 0.4 0.3 SUPPLY CURRENT (mA) 0.2 DNL (LSBs) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 50 100 150 CODES 200 250 300 1.25 1.55 1.50
SUPPLY CURRENT vs. TEMPERATURE (Rx MODE)
MAX1007-03
2.40 2.30 SUPPLY CURRENT (mA) 2.20 2.10 2.00 1.90 1.80 VDD = 2.85V VDD = 3.6V
VDD = 3.6V 1.45 1.40 1.35 1.30 VDD = 2.85V
-40
25 TEMPERATURE (C)
85
-40
25 TEMPERATURE (C)
85
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1007-04
PS BIAS VOLTAGE vs. TEMPERATURE
VDD = 3.6V 1.84 PS BIAS VOLTAGE (V) VDD = 2.85V 1.82
MAX1007-05
1.025 1.024 REFERENCE VOLTAGE (V) 1.023 1.022 VDD = 2.85V 1.021 1.020 1.019 -40 -5 25 55 85 TEMPERATURE (C) VDD = 3.6V
1.86
1.80
1.78
1.76 -40 -5 25 55 85 TEMPERATURE (C)
_______________________________________________________________________________________
5
Mobile-Radio Analog Controller MAX1007
Pin Description
PIN 1 NAME RPS FUNCTION Used to measure reverse-transmit power level. Only active in transmit mode when PKWDW = 1, SDAC[F/R] = Reverse. When not selected, this pin is internally pulled to AGND through a 200 switch. Used to measure forward power-sense class 2/3/4. Only active in transmit mode when GDAC[Power Class] = Class 2/3/4, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally pulled to AGND through a 200 switch. Used to measure forward power-sense level 1. Only active in transmit mode when GDAC[Power Class] = Class 1, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally pulled to AGND through a 200 switch. Buffered output of 7-bit DAC. Controls gain stage in up/down converter. Analog Supply Voltage Unbuffered output of 6-bit DAC. Used to control VCXO frequency. Analog Ground 1.028V Reference Voltage Output Buffered output of 7-bit DAC. Controls gain stage in external modulator block. Buffered output of 6-bit DAC. Controls negative gate bias voltage of external power amplifier. Software-Programmable Logic Output. Can be used to shut down external bias generator. Best-Antenna Digital Output. Result of preamble-switched diversity measurement (Figure 2). "0" indicates more power was sensed from period A with respect to period B. "1" means vice versa. Period A is sensed in the first 12 clock periods following the PSDWDW rising edge. Preamble-Switched Diversity Measurement-Control Signal (Figure 2). This pin has a 20k pull-down resistor to digital ground. Preamble-Switched Diversity Measurement Window (Figure 2). This pin has a 20k pull-down resistor to digital ground. RSSI/Power-Sense Measurement-Control Input (Figure 1) RSSI/Power-Sense Measurement-Window Digital Input (Figure 1) Serial-Data Output. Enabled when CS is low. Digital Ground Serial-Clock Input. Clock can be stopped and resumed at any time (40% to 60% duty cycle). Digital Supply Voltage Serial-Data Input Chip Select Input. Enables serial interface when low. Power-Sense Measurement Buffered-Bias Output Voltage. Active only during power sensing. Received-Signal Strength Indicator Analog Input for power-sense and antenna diversity measurements. Signal goes into peak-detector circuit and is sampled at the end of the measurement window by the 8-bit ADC. Only active in receive mode when PKWDW = 1. Peak-detector circuit can be bypassed by using CH1 as the ADC input.
2
FPS2
3 4 5 6 7 8 9 10 11 12
FPS1 SDAC AVDD XDAC AGND REF KDAC GDAC SDG BANT
13 14 15 16 17 18 19 20 21 22 23
PSDCTRL PSDWDW ADCCTRL PKWDW DOUT DGND SCLK DVDD DIN CS PSBIAS
24
RSSI
6
_______________________________________________________________________________________
Mobile-Radio Analog Controller MAX1007
STATE CONTROL SIGNALS PKWDW
A
B
C
2 CLOCKS 1 10 CLOCKS
7 CLOCKS
ADCCTRL INTERNAL SIGNALS ACTIVE ADC ADC CONVERSION RESET SWITCH FOR PS
8 CLOCKS
8 CLOCKS 6 CLOCKS 1 10 CLOCKS 1
Figure 1. RSSI/Power-Sense Control Signals
STATE ANTENNA SELECT (EXTERNALLY GENERATED) RSSI PSDWDW PSDCTRL 4 INTERNAL RESET 1 FIRST ANTENNA PERIOD A 8 CLOCKS
D
SECOND ANTENNA PERIOD B 4 INTERNAL RESET 2 OLD VALUE 9 CLOCKS COMPARE NEW VALUE 1
BANT
Figure 2. Antenna-Diversity Control Signals
_______________Detailed Description
The MAX1007 comprises several blocks for measuring and controlling radio-frequency (RF) signals. The measurement blocks, including power sense, antenna or preamble-switched diversity, and the analog-to-digital converter (ADC), allow the comparison of various RF inputs. The control blocks, including four digital-to-analog converters (DACs), digital outputs BANT and SDG, and the serial interface, aid frequency tuning and allow the optimization of transceiver gain under microprocessor control.
Power Sense
The power-sense circuit consists of a multiplexer (mux), a programmable gain amplifier (PGA), a peak detector, and a buffer. The circuit amplifies/attenuates the demodulated RF waveform, peak-holds the signal, and buffers the outputs to the ADC for power-sense measurement. The demodulation process with external circuitry for one channel is shown in Figures 3a and 3b. This circuit typically recovers the negative envelope of the RF waveform. The 1.87V PSBIAS voltage and the 100A current source are both generated by the MAX1007.
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7
Mobile-Radio Analog Controller MAX1007
In Figure 3b, the mux selects the signal from one of three input channels: RPS, FPS1, and FPS2. The PGA then amplifies or attenuates the input signal according to the signal power-class level and the transmission mode (forward or reverse) (Table 1). Three gain settings are provided in the PGA: -0.53, -0.44, and -6. The voltage range at the internal node PSOUT is equal to the ADC's input range. After the PGA, the signal is fed to a peak detector, which tracks the input and holds the positive peak voltage until the ADC starts a conversion.
Table 1. Data-Byte Definitions
A [2:0] 000 NAME XDAC D [7:0] Write [7,6]: [5:0]: Write 001 SDAC [6:0]: Write 010 KDAC [6:0]: Write [7,6]: 011 GDAC [6:0]: 100 101 110 111 ADC Read [7:0]: [7]: [7]: DESCRIPTION Reserved XDAC value [5:0]; LSB is bit 0, binary. F/R bit, defines forward or reverse power-sense measurement 0 = Reverse power-sense measurement; RPS pin 1 = Forward power-sense measurement; FPS1/FPS2 pin SDAC value [6:0]; LSB is bit 0, binary. ADC channel selection: 0 = Power sense or RSSI via peak-hold circuit connected to ADC (CH0) 1 = RSSI pin connected to ADC directly (CH1) KDAC value [6:0]; LSB is bit 0, binary. Power class: 00 = Class 1 01 = Class 2 10 = Class 3 11 = Class 4 GDAC value [5:0]; LSB is bit 0, binary. Reserved Reserved Reserved ADC value [7:0]; LSB is bit 0, binary.
PSBIAS 1.87V R5 300 C3 10pF AGND C1 10pF C4 1nF ISOURCE 100A
AVDD
50 TRANSMIT LINE OR 22nH INDUCTOR D1 R3 1k
R1
RPS FPS1 FPS2 RPS FPS1 C2 10pF FPS2 PGA PSOUT
RF INPUT
+ -
50
R2 50
AGND
Figure 3a. External Circuit for Envelope Detection (one channel)
8
Figure 3b. Power-Sense Block
_______________________________________________________________________________________
Mobile-Radio Analog Controller
RSSI
The RSSI input provides a filtered input and a direct input to the ADC. The filtered signal path consists of a unity-gain buffer, an RC lowpass filter, and a peak detector to condition the signal for the ADC. The lowpass filter's time constant is 10s (min). The mux at the ADC's input selects CH0 (filtered input) or CH1 (direct RSSI input).
Reference
The bandgap voltage reference supports several blocks of the MAX1007. The nominal 1.21V output is scaled and buffered for the power-sense bias, the PGA, the ADC, and the DACs. The PSBIAS output voltage is 1.87V nominal. The ADC reference is 1.028V. It is buffered to isolate switching noise and to allow external capacitor bypassing (0.014F to 0.05F) for AC stability. A buffered gain supplies all DACs with a nominal 2.42V reference voltage.
MAX1007
Control Timing
The power-sense circuit is activated by the externally generated PKWDW signal (Figure 1) when the MAX1007 is either in transmit or receive mode. When the PKWDW signal goes high, the entire power-sense circuit turns on. However, since the PGA is active only in the transmit mode, it remains shut down during RSSI power measurements to conserve power.
Digital-to-Analog Converters
All four DAC outputs are reset to zero at power-up. Preset DACs to output voltages other than zero in total shutdown mode and update DACs by settling the LD bit in the command byte.
XDAC
XDAC is a 6-bit voltage-output DAC intended to drive varactor diodes to tune a voltage-controlled crystal oscillator. The input is double-buffered for independent updates. The inverted R-2R ladder output is unbuffered since the load is strictly capacitive. The maximum output voltage is 2.42V nominal, and the maximum output resistance is 30k. The output is reset to zero at power-up and is active instantly. When XDAC is disabled, the DAC output is actively pulled to AGND.
Antenna Diversity
The antenna or preamble-switched diversity (PSD) circuit compares the signal amplitude presented at RSSI during two different time periods and latches the result at BANT (Best Antenna). The circuit consists of a dual track/hold (T/H) stage, a comparator, and an output latch (D flip-flop). The comparison begins with the signal from the first antenna applied to the RSSI pin (Figure 2). PSDWDW goes high, and the PSD circuit is turned on. A poweron-reset signal initializes the D flip-flop so that it always starts with BANT low. After 4 clocks to reset the peak detector, PSDCTRL goes high to start the measurement. The T/H stage acquires the signal for 8 clocks while PSDCTRL is high, then holds the peak value while the second antenna is switched externally to the RSSI pin and the T/H is zeroed. PSDCTRL goes low for another 4 clocks, then goes high to enable the peak detector again. The peak detector is active for another 8 clocks while the output is compared with the peak value for the first antenna. When PSDWDW goes low at the end of the comparison phase, the comparator's output is clocked into the D flip-flop. The D flip-flop's output, BANT, is low if the first antenna signal is greater than the second, and high if the second signal is greater than the first. PSDCTRL goes low one clock period after PSDWDW goes low to power down the PSD circuitry.
GDAC
GDAC is a 6-bit voltage-output DAC intended to control an external negative bias generator, such as the MAX840, for a GaAs amplifier. The digital input is doublebuffered. The inverted R-2R ladder output is buffered and can drive a 5k load. The maximum output voltage is 2.42V nominal. The DAC output is reset to zero at power-up and is active in standby. A programmable logic output (SDG) is provided to shut down the external bias generator.
SDAC and KDAC
SDAC and KDAC are 7-bit voltage-output DACs intended to tune power levels of an up/downconverter or a modulator. The digital inputs are double-buffered. The inverted R-2R ladder outputs are buffered and can drive 5k loads. The maximum output voltage is 2.42V nominal. The SDAC and KDAC DAC outputs are reset to zero at power-up.
Analog-to-Digital Converter
The ADC is an 8-bit, half-flash ADC with a T/H and two inputs (CH0, CH1). When selected, the acquisition time is 1.74s. The ADC input range is equal to the 1.028V internal reference.
Serial-Interface and Control Logic
The serial interface is a 4-wire implementation with CS, SCLK, and DIN inputs and a DOUT output. The hardware consists of a 7-bit command register, an 8-bit data input register, an 8-bit data output register, a counter, and control logic. Communication is framed in 16-bit words (8 command bits followed by 8 data bits)
9
_______________________________________________________________________________________
Mobile-Radio Analog Controller
READ CS t3 SCLK t4 DOUT t5 t8 t6 t7
WRITE SCLK t1 t2 DIN
LD is the software control to update the output registers. During a write operation, the addressed DAC's input buffer is updated. With LD reset to "0," the DAC register and DAC output remain unchanged. With LD set to "1," all DACs and power-class registers are simultaneously updated to the values in their input registers immediately after the last data bit (including DAC values, power-class bits, F/R bit, RSSI and ADC input selections, SDG, and power-down bits). After a 16-bit read cycle, pull CS high. The interface is now ready for a new command sequence. During a read operation, the ADC conversion result is output to DOUT. With LD set to "1," all other outputs and powerclass registers are also updated.
MAX1007
Figure 4a. Read/Write Detailed Interface Timing
by the counter. Data is clocked into DIN or the falling edge of SCLK, and is clocked out of DOUT on SCLK's rising edge. The serial interface is always active. The SCLK and DIN idle state is low (Figure 4). The first "1" clocked in after CS goes low is the start bit, signifying the beginning of a 16-bit data word. The command and data input registers are cleared and the counter is started. The next 7 bits are latched in the command register.
Write Command The 8 data bits are latched in the data input register. The command byte is decoded, and the data bits are transferred to the appropriate registers. Read Command After the command byte is decoded, the last 8 clocks output data, MSB first, from the ADC output register to DOUT (Figure 4b). After a 16-bit read cycle, pull CS high. The interface is now ready for a new command sequence.
To minimize the delay between the power-sense measurement and the ADC output, program a `READ ADC' command prior to making the power-sense measurement and clock out the data as soon as the conversion is complete (Figure 4b). This reduces the delay by 8 clock cycles. To minimize the delay between the power-sense measurement and the ADC output, program a "READ ADC" command prior to making the power-sense measurement and clock out the data as soon as the conversion is complete (Figure 4b). This reduces the delay by F clock cycles.
Command Byte The command byte (Figure 4d) consists of three address bits (A2, A1, A0), two power-mode bits (RxEN, TxEN), a shutdown control bit (SD), and a load data bit (LD). Table 1 lists the address and data-byte definitions.
SD is the software control for the GaAs FET bias generator shutdown pin and GDAC. Resetting SD to "0" causes SDG to go low and disables GDAC. The SDG output is updated if LD is set high.
CS SCLK ACTIVE ADC DOUT WRITE A "READ ADC" COMMAND POWER-SENSE MEASUREMENTS CLOCK COMMAND BYTE INTO DIN t9 ADC CONVERSION DATA CLOCK OUT CONVERSION RESULT CLOCK CONVERSION DATA ONTO DOUT
Figure 4b. Clock Command Conversion
10 ______________________________________________________________________________________
Mobile-Radio Analog Controller
Table 2. Power Modes
ADCCTRL RSSI RPS FPS1 FPS2 PSBIAS RF INPUTS t10
MAX1007
RxEN, TxEN 00 01 10
t11
DESCRIPTION Total shutdown Transmit mode, all DACs enabled Receive mode, SDAC and GDAC outputs disabled Standby: REF, GDAC, and XDAC enabled. Rest of IC is shut down.
PSDWDW
11
VALID
BANT
OLD DATA
Figure 4c. Power-Sense/Best-Antenna Detailed Interface
WRITE
CS SCLK DIN START A2 A1 A0 RxEN TxEN SD LD D7 D6 D5 D4 D3 D2 D1 D0
READ
CS SCLK DIN START A2
COMMAND BYTE
A1
A0 RxEN TxEN SD
LD
COMMAND BYTE DOUT D7 D6 D5 D4 D3 D2 D1 D0
Figure 4d. Serial-Interface Timing
Applications Information
Precautions must be taken to minimize RF coupling through the IC.
Power-Supply Bypassing and Ground Management
Optimum system performance is obtained with printed circuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected together at the low-impedance power-supply source. Bypass AVDD with a 0.1F ceramic capacitor connected between AVDD and AGND. Mount it with short leads close to the device. Similarly bypass DVDD with a 0.1F ceramic capacitor connected between DV DD and DGND. Ferrite beads may also be used to further isolate the analog and digital power supplies.
Shutdown Modes
At power-up, the device initializes in total shutdown mode. The digital interface is always active. Table 2 describes the various power modes available. When the PGA is not on (in shutdown, standby, or receive mode, or when PKWDW is low), the PS input pins (RPS, FPS1, FPS2) are pulled down to ground. To minimize RF coupling, the unselected channels are also pulled down to ground when the circuit is active. The current source and the 1.87V PSBIAS voltage generator are turned on only when the device is performing the transmit power-sense measurement.
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11
Mobile-Radio Analog Controller MAX1007
Pin Configuration
TOP VIEW
RPS 1 FPS2 2 FPS1 3 SDAC 4 AVDD 5 XDAC 6 AGND 7 REF 8 KDAC 9 GDAC 10 SDG 11 BANT 12 24 RSSI 23 PSBIAS 22 CS 21 DIN
Chip Information
TRANSISTOR COUNT: 6744
MAX1007
20 DVDD 19 SCLK 18 DGND 17 DOUT 16 PKWDW 15 ADCCTRL 14 PSDWDW 13 PSDCTRL
SSOP
________________________________________________________Package Information
SSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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